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The Hardware Abstraction Layer that was introduced to RISC OS 5 means that RISC OS is no longer dependent on a fixed set of core chips. Thus this section of the manual will describe the bare minimum hardware required to support RISC OS, and then provide links to more detailed information about actual hardware platforms that run RISC OS.
The ARM processor must implement version 3 (or above) of the ARM architecture, and must support the ARM instruction set. Support for the Thumb instruction set is not required. RISC OS will use the processor solely in 32bit mode; support for 26bit mode is not required. Finally, the processor must have an integrated MMU.
TODO – EXPAND WITH MORE DETAILS, SIMILAR TO THE ARCHIMEDES HARDWARE PAGE
Like previous versions of RISC OS, RISC OS 5 only requires a small amount of memory to be functional. The exact minimum is currently unknown, but it is expected to be around 1MB.
The only other hardware that RISC OS absolutely requires is a timer capable of generating 100Hz interrupts on the processor’s IRQ line.
All other hardware (keyboard, mouse, audio, video, disc drives, etc.) is optional and not strictly required for a working ROM image. Drivers built into the machine-specific HAL and module chain are used to talk to this additional hardware, and so by customising the ROM image appropriately almost any type of hardware can be used for I/O devices.
At present there are six basic machine types that have successfully run versions of RISC OS 5: