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Many hardware designs have an IIC bus. Often, it is used only to support non-volatile memory, but in other systems TV tuners, TV modulators, microcontrollers, and arbitrary expansion cards may be fitted.
Low-level and high level APIs are defined. An arbitrary number of buses is supported, and each can be controlled by either the low or high level API. The OS should normally only use one fixed API on each bus – mixing APIs is unpredictable.
The low-level API requires the OS to control the two lines of the bus directly. The high-level API currently covers version 2.1 of the IIC protocol, and allows high-level transactions to be performed.
It is expected that a HAL will always provide the low-level API on each bus, where possible in hardware. Using this, the OS can provide Fast mode single or multi-master operation. The HAL may wish to provide the high-level API where a dedicated IIC port with hardware assistance is available; this will further permit High-speed and slave operation.
As it is possible that some HAL APIs (eg NVMemory), although abstracted at this API layer, are still actually an IIC device, a matching set of high-level IIC calls are provided in the OS. These give the HAL access to the OS IIC engine, which will make low-level HAL calls. This saves the HAL from implementing the full IIC protocol. To illustrate this diagramatically:
+----------+ NVMem_Read +------------+ NVMemoryRead +------------+ | | ---------> | | ------------> | | | App | | OS | IICTransmit | HAL | | | | | <------------ | | | | | | IICSetLines | | | | | | ------------> | | +----------+ +------------+ +------------+
Note that all the HAL IIC calls are for internal OS use only. User programs should use the OS_IICOp SWI instead of interacting with the HAL directly.
The low-level calls should be instantaneous. Interrupt status may not be altered.
IICLines structure
The high-level interface process a single transfer at a time (from the initial START to the STOP). It is designed to support background operations.