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The HAL should provide at least 240 bytes of non-volatile memory. If no non-volatile memory is available, the HAL may provide fake NVRAM contents suitable for RISC OS – however, it is preferable that the HAL just state that NVRAM is not available, and RISC OS will act as though a CMOS reset has been performed every reset.
NVRAM is typically implemented as an IIC device, so the calls are permitted to be slow, and to enable interrupts. The HAL is not expected to cache contents.
If the HAL has no particular knowledge of NVMemory, then it may just say that “NVMemory is on IIC”, and the OS will probe for CMOS/EEPROM devices on the IIC bus.
Items marked ¶ are internal calls for OS use only; their functionality and availability is subject to change without warning. User programs interested in using these calls should instead use the equivalent RISC OS SWI call (if available).