Showing changes from revision #3 to #4:
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Currently, only API versions 0 and 1 are defined.
struct dmalistchannel { /* Public interface */ struct device dev; struct dmalistchannelfeatures *(*Features)(struct dmachannel *); dmacontroller *controller; void (*Abort)(struct dmachannel *); void (*SetOptions)(struct dmachannel *, uint32_t flags, uint32_t address); void (*SetListTransfer)(struct dmachannel *, uint32_t blockphy, void *blocklog, uint32_t nentries, uint32_t length); uint32_t (*ListTransferProgress)(struct dmachannel *); uint32_t (*ListTransferStatus)(struct dmachannel *); uint32_t (*CurtailListTransfer)(struct dmachannel *, uint32_t minimum); }
dev is the standard HAL Device descriptor. The address field is not used. Channels are activated/deactivated around each transfer (and are deactivated when a transfer is suspended). Interrupts are used to detect transfer termination, and to trigger sync callbacks. If the device provides no interrupt, the device is interrogated from a TickerV routine instead.
dev.Activate, dev.Deactivate_, and_dev.Reset are handled similarly to buffer-type DMA channel
Features returns a pointer to the following data structure:
struct dmalistchannelfeatures { uint32_t flags; uint32_t blocksize; uint32_t blockalign; uint32_t blockbound; uint32_t maxtransfers; uint32_t transferlimit; uint32_t transferbound; }
Defined flags bits are as followed:
Bit | Flag | Meaning when set |
---|---|---|
1 | DMAFeaturesFlag_NotCircular | Channel does not support circular transfers |
2 | DMAFeaturesFlag_NotInfinite | Channel does not support infinite transfers |
3 | DMAFeaturesFlag_NoSyncIRQs | Channel does not generate interrupts on completion of each entry in the transfer descriptors block, so there is no benefit to be gained by splitting descriptors at multiples of the sync gap (sync gap splitting is done when this bit is clear, to provide more accurate sync callbacks) |
Flag bits not mentioned are reserved and must be set to zero.
Other entries in the structure are as follows:
controller points to this channel’s DMA controller device
Abort should be considered a “forced” version of dev.Deactivate, and is only used for SWI DMA_TerminateTransfer. The call must not block, but the values subsequently returned from TransferState and Status are allowed to report inaccurate results, providing they underestimate the progress of the transfer.
SetOptions is the same as for buffer-type DMA channel devices, with the addition of one extra flag:
Bit(s) | Meaning |
---|---|
15 | Bit set => Transfer is circular |
SetListTransfer initiates the transfer according t o the transfer descriptors block:
ListTransferProgress returns the number of bytes transferred since the transfer was initiated. If this cannot be determined exactly, an underestimate should be returned.
ListTransferStatus returns status flags for the current channel:
Bit | Meaning |
---|---|
0 | Bit set => An error has occured accessing memory (e.g. bus abort) since the transfer was initiated. |
1 | Bit set => An error has occured accessing the device (e.g. transfer size mismatch) since the transfer was started. |
Other bits are reserved and should be zero.
CurtailListTransfer requests that a transfer in progress be shortened as much as possible subject to normal termination conditions (e.g. raising the TC line). The call need not block. For infinite transfers, there is a minimum requirement that this makes the transfer finite. minimum specifies the minimum number of bytes that must still be transferred (as returned from the DMASync callback). Returns the number of bytes that will have been transferred when the transfer terminates.
API version 1 extends the set of flags returned by Features:
Bit | Flag | Meaning when set |
---|---|---|
4 | DMAFeaturesFlag_NoInitIRQ | Channel doesn’t generate an IRQ if Activate is called when the channel has no pending transfers |
HALDeviceSysPeri_DMAL is supported by the trunk branch version of the DMAManager module.DMAManager module.
Device ID | Description | Implemented in |
---|---|---|
HALDeviceID_DMAL_M5229 | Acer M5229 ATA controller bus master primary channel | HAL.Tungsten.s.ATA |
Acer M5229 ATA controller bus master secondary channel | ||
HALDeviceID_DMAL_BCM2835 | BCM2835 DMA channel | HAL.BCM2835.s.DMA |