HAL_FIQEnable (changes)
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Hardware Abstraction Layer
HAL entry points from RISC OS
ยป HAL_FIQEnable
HAL_FIQEnable
(HAL entry #6)
int HAL_FIQEnable(int device)
| Entry | |
|---|---|
| device | Device number to enable interrupts for |
| Exit | |
|---|---|
| 0 | Interrupts were previously disabled for this device |
| non-zero | Interrupts were previously enabled for this device |
Use
Modifies the interrupt controller so that the ARM receives an FIQ when device generates an interrupt.
Note: Behaviour is undefined if an attempt is made to enable both IRQ and FIQ for the same device.For some interrupt controllers, such as IOMD, any given interrupt line can only operate as an IRQ or a FIQ, and device numbers are allocated independently for each. In these cases, this call simply unmasks the interrupt in the interrupt controller.
Other controllers, such as OMAP, support steering of each interrupt line between IRQ and FIQ independently, and one number space is used for device numbers across both types of interrupt. In these cases, this call additionally configures the interrupt to trigger a FIQ rather than an IRQ. Note: Behaviour is undefined if an attempt is made to enable both IRQ and FIQ for the same device.
See also
Information sources: Kernel.Docs.HAL.MoreEnts, HAL.Tungsten.s.Interrupts, HAL.OMAP3.s.Interrupts in CVS
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