Memory Cache Policies (changes)
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Programmer's OS Reference SWI Manuals Calls
» Part OS_ReadMemMapEntries 15 – SWI Calls
» OS Memory Map Request Block
» OS_ReadMemMapEntries Page Access
» Memory Cache PoliciesMemory Map Request Block
» Page Access
» Memory Cache Policies
Memory Cache Policies
Compared to previous versions of RISC OS, RISC OS 5 has extended support for specifying the cache policy of memory regions. The cache policy is specified through a combination of bits 4-5 and bits 12-14 of the page access flags.
Bit 4 (the nonbufferable bit) and bit 5 (the noncacheable bit) specify the basic cache policy that’s used. The policy number specified in bits 12-14 then modify this policy, as described in the tables below. Each policy also has a fallback policy listed; the kernel will automatically try successive fallback policies until a supported policy is found.
CB (cacheable + bufferable) policies
| Policy | Meaning | Fallback policy |
|---|---|---|
| 0 | OS decides policy (Writeback if available, or write alloc for areas mapped by HAL) | - |
| 1 | Writethrough cacheable, read allocate. | NCB policy 3 (merging-idempotent) |
| 2 | Writeback cacheable, read allocate. | CB policy 1 (writethrough) |
| 3 | Writeback cacheable, write allocate. | CB policy 2 (writeback cacheable, read allocate) |
| 4 | Alternative D-cache (XScale/StrongARM mini D-cache on pre-ARMv6, or inner write-through + outer write-back on ARMv6+) | CB policy 0 (default policy) |
| 5-7 | Reserved | - |
NCB (non-cacheable + bufferable) policies
| Policy | Meaning | Fallback policy |
|---|---|---|
| 0 | OS decides buffer policy (currently, merging-idempotent by default) | - |
| 1 | Non-merging write buffer. | NCNB |
| 2 | Merging write buffer. | NCB policy 1 (Non-merging write buffer) |
| 3 | Merging-idempotent (merging write buffer to RAM-like device where reads & writes are idempotent) | NCB policy 2 (Merging write buffer) |
| 4-7 | Reserved | - |
CNB (cacheable + non-bufferable) policies
| Policy | Meaning | Fallback policy |
|---|---|---|
| 0 | OS decides cache policy (currently, writethrough by default) | - |
| 1 | Writethrough cache, non-buffered. | NCNB |
| 2 | Writeback cache, non-buffered. | CNB policy 1 (Writethrough cache, non-buffered) |
| 3-7 | Reserved | - |
NCNB (non-cacheable, non-bufferable) policies
| Policy | Meaning | Fallback policy |
|---|---|---|
| 0 | Default policy | - |
| 1-7 | Reserved | - |
Relationship to VMSAv6 memory types
On ARMv6 and later CPUs, RISC OS uses the VMSA memory model, which defines three basic types of memory: Normal, Device, and Strongly-Ordered (see the ARM ARM for full details). These memory types provide a greater level of control than the traditional cacheable+bufferable flags, and so for some purposes a non-default cache policy must be used to make sure the correct memory type is used.
Starting with RISC OS 5.23, cache policies map to VMSAv6 memory types as follows:
- All CB types map to VMSA Normal memory (cacheable or non-cacheable, depending on support for the specific cache policy)
- As standard, VMSA doesn’t provide support for a CNB memory type, and so CNB types currently map to Strongly-Ordered. Use of CNB type is discouraged unless you know that a particular system supports it.
- All NCNB types map to VMSA Strongly-Ordered memory
- NCB with cache policies 1 and 2 map to VMSA Device memory
- NCB with other cache policies (including the default) map to VMSA Normal, non-cacheable memory
On previous versions of RISC OS 5 all NCB memory would have mapped to the VMSA Device type, and CNB would have been erroneously treated as Normal write-through cacheable (i.e. not write-through non-bufferable). Additionally, on RISC OS 5.23 and above, making memory temporarily uncacheable via OS_Memory 0 will now cause it to retain its VMSA memory type – only the cacheability will be affected (previously, making e.g. CB uncacheable would have transformed it from Normal to Device)
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