OMAP3 Hardware (changes)

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» OMAP3 Hardware

Overview

The “Beagle” ROM image is designed to run on the BeagleBoard and other similar devices. Specifically, the machine must use a Texas Instruments OMAP3 system-on-chip, and a Texas Instruments TPS65950 (or compatible – e.g. TWL4030) companion IC. These two chips provide the majority of the subsystems which the ROM image expects to exist. However not all OMAP3-based boards are identical, and so in order to support a new board type some minor adjustments may need to be made to the ROM image, with regards regard to its assumptions aboutRAM parameters, GPIO usage or I^2^C I usage.²C usage.

The OMAP3 system-on-chip

The OMAP3 range of system-on-chips is designed primarily for use in low-power mobile computing devices – e.g. smartphones, PDAs, tablets and netbooks. It contains a number of subsystems:

MPU Subsystem

The microprocessor unit (MPU) subsystem contains the ARM core, caches, and interrupt controller.

A Cortex-A8 ARM core is used, supporting the ARMv7 architecture, including VFPv3/NEON SIMD. The core has a split L1 cache (16KB instruction, 16KB data), and 256KB L2 cache.

The interrupt controller manages 96 interrupt lines, allowing each to be mapped to either the IRQ or FIQ line on the ARM core, or masked and disabled entirely.

IVA2.2 Subsystem

The IVA2.2 subsystem is only present in certain models of the OMAP3. If present, it contains a second CPU core, based around the Texas Instruments TMS320DMC64x+ VLIW DSP (commonly referred to as the “C64x”). With its own caches, interrupt controller, and DMA controller, the IVA2.2 subsystem is capable of decoding 720p compressed video.

On-Chip Memory

The OMAP3 contains 112KB of ROM, containing the initial bootloader, and 64KB of SRAM. The SRAM is currently ignored by RISC OS.

External Memory Interfaces

There are two external memory interfaces:

• The General-purpose memory controller (GPMC) is used to interface the chip with NOR and NAND flash, as well as some types of peripheral hardware (most commonly Ethernet controllers).
• The SDRAM controller (SDRC) is used to interface the chip with up to 2GB of M-SDR or LPDDR SDRAM.

DMA controllers

There are four DMA controllers in a typical OMAP3 device:

• The system DMA controller (sDMA), a flexible multi-channel DMA controller that RISC OS uses for tasks such as audio DMA, accelerating graphics copies and fills, etc.
• The enhanced DMA controller (EDMA), embedded in the IVA2.2 subsystem (if present)
• The display DMA controller, used by the display hardware to read pixel data.
• The USB HS DMA, used by the USB subsystem.

Multimedia Accelerators

Several multimedia accelerators are present:

• 2D and 3D graphics accelerator (SGX). Only present on certain models, the SGX supports programmable shaders, OpenGL 2.0, and can be used for decoding/encoding of common video formats including H.264, H.263, MPEG4 (SP) and WMV9.
• Camera interface subsystem (ISP). Supports most of the raw image sensors available in the market.
• Display interface subsystem. Supports display sizes up to 2048×2048, hardware overlays, display rotation/scaling, and colour-space conversion. Multiple physical interfaces and protocols are supported, including direct connection with LCD panels, and output of analogue S-Video/composite signals.

Security

Certain models of OMAP3 include hardware implementations of common encryption/hashing algorithms such as DES, SHA1/2, MD5, AES and PKA.

Peripherals

The OMAP3 contains many “peripheral” devices:

• 5 multi-channel buffered serial ports (McBSPs), used to perform reliable serial communication with external devices (e.g. audio codecs)
• 4 multi-channel serial port interfaces (McSPI), allowing interface with SPI devices
• High-speed multi-port USB host controller, configurable for EHCI (USB 2.0) or OHCI (USB 1.0) operation
• High-speed USB OTG controller
• HDQ/1-Wire interface
• 3 UARTs, including IrDA and CIR support
• 3 high-speed I^2^S I interfaces²S interfaces
• MMC/SDIO memory card interface
• 12 general-purpose timers
• 3 watchdog timers
• 1 32kHz clock timer
• Six GPIO controllers addressing a total of 192 GPIO pins (although the number of available pins depends on how the chip is packaged)
• 6 mailboxes for inter-processor communication

The TPS65950 chip

To function correctly correctly, the OMAP3 requires a companion chip. This companion chip performs important tasks related to power management, and communicates with the OMAP3 via the use of a fourth, software-inaccessible I^2^C I connection. In the case of the TPS65950 (and similar software-compatible chips, e.g. TWL4030), several additional functions are provided. These additional functions are typically accessed via one of the three software-accessible I^2^C interfaces on the²C connection. In the case of the TPS65950 (and similar software-compatible chips, e.g. TWL4030), several additional functions are provided. These additional functions are typically accessed via one of the three software-accessible I²C interfaces on the OMAP.

• Audio codec
• Battery charger
• USB 2.0 OTG transceiver
• Real-time clock with support for operation from backup battery
• Additional features including LED driver, GPIO, ADC, PWM, keypad interface, and thermal shutdown protection/hot-die detection.

See also

• Detailed information about the Cortex-A8 port of RISC OS