OS_ClaimProcessorVector (changes)

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OS SWI Calls

» OS_ClaimProcessorVector

OS_ClaimProcessorVector

(SWI &69)

Use

The purpose of this call is to claim a processor vector.

Notes

This call is used to allow low-level code to claim the ARM’s hardware vectors vectors, which are called when interrupts and aborts occur.

The address of your routine must be provided on release to ensure claims and releases happen in the correct order. If the address currently on the vector differs from that in R2, an error is returned.

The FIQ vector cannot be claimed through this call. Instead, Service_ClaimFIQ or Service_ClaimFIQinBackground must be used.

Routines installed via OS_ClaimProcessorVector are entered directly from the corresponding hardware vector. This means that:

• On 26bit OS versions, they will be entered in a 32bit CPU mode.
• Data and prefetch abort handlers need to be careful about accessing application space; if lazy task swapping is enabled enabled, this may trigger a recursive abort, potentially leaving the machine stuck in an abort loop.
• On ARMv6 and newer, care is needed to ensure the “exclusive monitor” is left in a safe state. See the ARM ARM or the Hardware Vectors documentation for more detail.

This SWI is only available on RISC OS 3.5 and later. To claim a processor vector on earlier OS versions, you must directly patch the processor vector table at &0. If your code needs to pass on to the previous claimant claimant, then care will be needed to make sure you decode the old handler instruction correctly (typically it will either be a branch instruction or a PC-relativeLDR of the PC)

See also

• Processor Vector Numbers
• Service_ClaimFIQ
• Service_ClaimFIQinBackground