OS_MMUControl 0 (changes)

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Programmer's OS Reference SWI Manuals Calls

» Part OS_MMUControl 15 – SWI Calls

» OS_MMUControl 0OS

OS_MMUControl 0

(SWI &6B)

Use

The purpose of this call is to allow the value of the ARM system control register to be read or modified.

Notes

The bits in R1 and R2 correspond directly to those in the system control register; therefore the exact assignment will differ between ARM versions.

Use of this call is discouraged, except for the purposes of enabling and disabling the caches – for which this SWI will perform the correct cache clean/invalidation sequences as required by the architecture. On all ARMv3+ ARMs to date, bit 2 controls the data/unified cache and bit 12 controls the instruction cache.

The OS may restrict the values of some of the flags in order to ensure correct operation of the system. However there are many potentially unsafe values which are not checked for, so care must be taken not to rely on the OS restricting the settings automatically.

See also

• OS_MMUControl