OS_MMUControl 2 (changes)

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Programmer's OS Reference SWI Manuals Calls

» Part OS_MMUControl 15 – SWI Calls

» OS_MMUControl 2OS

OS_MMUControl 2

(SWI &6B)

Use

The purpose of this call is to read the address of one of the kernels “ARMop” routines. The ARMops are the low-level cache/TLB maintenance routines that the OS uses, and calling them directly can result in higher performance than calling equivalent SWIs such as OS_MMUControl 1.

Notes

The available ARMops are as follows:

Requesting an unknown ARMop will result in an error. Unused ARMops (e.g. IMB on CPU with unified cache) will return a pointer to a dummy routine which does nothing – this can be detected as it will be a single MOV pc,lr instruction.

The general rules for register usage and preservation in calling these ARMops are:

• Any parameters are passed in R0,R1 etc. as required
• SP must be a valid stack pointer, with at least 16 words available
• Return address must be in LR
• The CPU must be in a privileged mode
• ARMops are allowed to corrupt R0, LR, and the PSR status flags. All other registers (unless used for return values) are preserved.

All ARMops are re-entrant, and it is preferred to call them with interrupts enabled (cache clean operations can be lengthy).

Note that where register values are given as logical addresses, these are RISC OS logical addresses. The equivalent ARM terminology is virtual address (VA), or modified virtual address (MVA) for architectures with the fast context switch extension.

Note also that where cache invalidation is required, it is implicit that any associated operations for a particular ARM will be performed also. The most obvious example is for an ARM with branch prediction, where it may be necessary to invalidate a branch cache anywhere where instruction cache invalidation is to be performed.

This call was first introduced with RISC OS 5.23

See also

• OS_MMUControl 1