OS_PlatformFeatures 0 Flags (changes)
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OS SWI Calls
» OS_PlatformFeatures
» OS_PlatformFeatures 0
» Flags
Flags
| Bit | Meaning when set |
|---|---|
| 0 | You must tell the OS when a code area changes (OS_SynchroniseCodeAreas) |
| 1 | Enabling then disabling interrupts does not allow them a chance to occur (Use interrupt trigger routine returned in R1) |
| 2 | Hardware vectors are only readable in 32 bit mode |
| 3 | When storing PC, PC+8 is stored (not PC+12) |
| 4 | Data aborts occur with ‘full early’ timing (Base restored abort model) |
| 5 | CPU has split instruction & data caches |
| 6 | OS is 32-bit |
| 7 | CPU doesn’t support 26-bit modes |
| 8 | CPU has ‘M’ extensions (long multiply – UMULL, etc.) |
| 9 | CPU supports Thumb mode |
| 10 | CPU has ‘E’ DSP extensions (QADD, etc.) |
| 11 | SWP/SWPB are not available (see notes) |
| 12 | CPU supports LDR/STREX semaphores |
| 13 | CPU supports CLREX and LDR/STREX[B|H|D] semaphores |
| 14 | D-cache can’t be disabled safely and OS_MMUControl 0 won’t allow it |
| 15 | CPU supports extended small page L2 descriptors |
| 16 | CPU doesn’t have a Drain Write Buffer instruction |
| 17 | Aborts don’t correctly follow the documented abort model (e.g. StrongARM pre rev-T; prevents lazy task swapping from being used) |
| 18 | CPU is an XScale |
| 19 | XScale JTAG is connected |
| 20 | High processor vectors are in use (vectors at &FFFF0000 instead of &0). See also OS_PlatformFeatures 32 |
| 21 | Some of the RAM has a physical address of 2^32 or higher. If set, software should prefer to use APIs which use 64bit physical addresses; older APIs which only support 32bit physical addresses will have limited functionality |
| Physical pages are not available to the OS (operations on physical page numbers will fail) | |
| 23-30 | Reserved |
| 31 | Probing for additional OS_PlatformFeatures reason codes is supported (see notes) |
SWP/SWPB availability
Bit 11 is set to indicate that SWP/SWPB definitely aren’t available, in which case LDREX/STREX will generally be available instead.
When bit 11 is clear, and provided you are on RISC OS 3.5 or later OR CallASWI version 0.12 or later is in use, then SWP/SWPB definitely are available.
If you are on an OS version which supports the Archimedes (i.e. pre-RISC OS 3.5), and CallASWI is older than 0.12, then the information returned by bit 11 will be incorrect for ARM2 machines, as SWP/SWPB were introduced with a later architecture version (ARMv2a – as used by the ARM250 and ARM3 CPUs). If your code is running on an old OS version and needs to manually detect whether SWP/SWPB are available then the technique described in Application Note 276 is the suggested method to use.
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