OS_PlatformFeatures 34 Flags (changes)
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» OS_PlatformFeatures
» OS_PlatformFeatures 34
» Flags
Flags
| Bit | Meaning when set |
|---|---|
| 0 | AESE, AESD, AESMC, AESIMC instructions are supported |
| 1 | BFC, BFI, SBFX, UBFX instructions are supported |
| 2 | BKPT instruction is supported |
| 3 | BLX instruction is supported |
| 4 | BX instruction is supported |
| 5 | CLREX, LDREXB, LDREXH, STREXB, STREXH instructions are supported |
| 6 | CLZ instruction is supported |
| 7 | CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, CRC32CW instructions are supported |
| 8 | DMB, DSB, ISB instructions are supported |
| 9 | ERET and the MRS/MSR (banked register) instructions are supported |
| 10 | HVC instruction is supported |
| 11 | “MOV pc, xx” class of instructions perform interworking branches |
| 12 | Load-acquire/store-release instructions are supported (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, LDAEXD, STLB, STLH, STL, STLEXB, STLEXH, STLEX, STLEXD) |
| 13 | LDM/STM are continuable4 |
| 14 | LDM/STM are noninterruptible4 |
| 15 | LDM/STM are restartable4 |
| 16 | LDRD, STRD instructions are supported |
| 17 | LDREXD, STREXD instructions are supported |
| 18 | LDREX, STREX instructions are supported |
| 19 | LDRHT, LDRSBT, LDRSHT, STRHT instructions are supported |
| 20 | LDRH, LDRSH, STRH instructions are supported1 |
| 21 | LDRSB instruction is supported |
| 22 | LDR/STR with writeback and Rd == Rn is not allowed. Applies to all load/store single instructions. |
| 23 | MLS instruction is supported |
| 24 | MOVW, MOVT instructions are supported |
| 25 | MRS, MSR instructions are supported (except banked register version, see flag 9) |
| 26 | MUL with Rd == Rn is not allowed. Applies to MUL, MLA, SMLAL, SMULL, UMLAL, UMULL |
| 27 | MULS, MLAS corrupt C flag. SMLALS, SMULLS, UMLALS, UMULLS corrupt C & V flags. If this feature flag is clear, the corresponding PSR flags are preserved. |
| 28 | NOP and other NOP-compatible hints are supported. See flag 57 for WFE.2 |
| 29 | PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, UADD16, UADD8, UASX, UHADD16, UADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX instructions are supported |
| 30 | PLD instruction is supported |
| 31 | PLDW instruction is supported |
| 32 | PLI instruction is supported |
| 33 | PSR ‘GE’ flags are supported |
| 34 | PSR ‘Q’ flag is supported |
| 35 | QADD, QDADD, QDSUB, QSUB instructions are supported |
| 36 | RBIT instruction is supported |
| 37 | REV, REV16, REVSH instructions are supported |
| 38 | SEVL instruction is supported |
| 39 | SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, SHA1SU1 instructions are supported |
| 40 | SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions are supported |
| 41 | SMC instruction is supported |
| 42 | SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions are supported |
| 43 | SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, SMUSDX instructions are supported |
| 44 | SMULL, SMLAL instructions are supported |
| 45 | SRS, RFE, CPS instructions are supported |
| 46 | SSAT, USAT instructions are supported |
| 47 | SWP, SWPB instructions are fully supported |
| 48 | SWP, SWPB are supported, but are only guaranteed to be atomic in uniprocessor environments |
| 49 | SXTAB, SXTAH, UXTAB, UXTAH instructions are supported |
| 50 | SXTB16, SXTAB16, UXTB16, UXTAB16 instructions are supported |
| 51 | SXTB, SXTH, UXTB, UXTH instructions are supported |
| 52 | SYS processor mode is supported |
| 53 | TEQP, TSTP, CMPP, CMNP instructions are supported |
| 54 | UDIV, SDIV instructions are supported |
| 55 | UMAAL instruction is supported |
| 56 | UMULL, UMLAL instructions are supported |
| 57 | WFE instruction is supported2 |
| 58 | Rotated loads are supported3 |
| 59 | Unaligned loads/stores are supported3 |
| 60 | CP15 IFAR register implemented |
| 61 | CP15 IFSR register implemented |
| 62 | CP15 AIFSR register implemented |
| 63 | CP15 DFAR & DFSR registers are writable |
| 64 | CP15 ADFSR register implemented |
Notes
Unless otherwise noted, instruction-related flags only apply to the use of that instruction from ARM CPU modes; information about Thumb modes is not reported.
VFP/NEON instruction availability can be determined via VFPSupport_Features.
1 Halfword load/store:
Halfword load/store instructions will only be reported as supported if the machines bus architecture supports them (e.g. the flag will never be set on a RiscPC)
2 WFE and WFI:
WFE (flag 57) is separated out from the other NOP/hint instructions (28) in order to account for the fact that uniprocessor systems typically support WFE by implementing it as a pure NOP – i.e. they do not enter a low-power state. On such systems it is therefore more favourable to use Portable_Idle when idling the CPU is desired. Note also that the WFI instruction should not be used directly (use Portable_Idle instead); even if the NOP hints are supported there’s no guarantee that the WFI instruction is supported (another instruction may be in use instead), or there may be errata or other machine-specific behaviours which need to be dealt with.
3 Memory access alignment modes:
The load/store alignment mode information returned by flags 58 and 59 indicates the capabilities of the CPU. By itself, the information does not indicate what the currently selected alignment mode is, nor does it guarantee that the OS will function if any given alignment mode is selected. If a program wishes to (e.g.) select between three different variants of a routine (rotated, unaligned, and aligned) then it should use OS_ReadSysInfo 8 to determine the alignment mode that the OS ROM was built for, and use the routine variant which matches that.
4 LDM/STM interruptibility
Flags 13-15 indicate the behaviour of LDM/STM instructions when the system is running in low interrupt latency mode (as configured in the system control register). Only one of the flags will be set.
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