Showing changes from revision #5 to #6:
Added | Removed | Changed
# | Vector |
---|---|
0 | Branch through zero |
1 | Undefined instruction |
2 | SWI executed |
3 | Prefetch abort |
4 | Data abort |
5 | Address exception (ARMv2), Hypervisor trap (ARMv7VE, not used by RISC OS) |
6 | IRQ |