RISCOS_Start (changes)
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Hardware Abstraction Layer
» RISC OS entry points from HAL
» RISCOS_Start
RISCOS_Start
(OS entry #2)
void RISCOS_Start(unsigned int flags, int *riscos_header,
int *hal_descriptor, void *ref)
| Entry | |
|---|---|
| flags | Bit 0: power on reset |
| Bit 1: CMOS reset inhibited (eg protection link on Risc PC) | |
| Bit 2: perform a CMOS reset (if bit 1 clear and bit 0 set – eg front panel button held down on an NC) | |
| Bit 3: there is no CMOS (the Kernel must use a RAM cache) | |
| Bit 4: the RAM has already been cleared to zero | |
| riscos_header | Pointer to OS image header |
| hal_descriptor | Pointer to HAL descriptor |
| ref | Reference value that was returned by the last call to RISCOS_AddRAM |
| SVC32 mode | |
| MMU and data caches off | |
| IRQs and FIQs disabled |
| Exit | |
|---|---|
| - | This call does not return |
Use
This routine must be called after all calls to RISCOS_AddRAM have been completed. It does not return. Future calls back to the HAL are via the HAL entry table, after the MMU has been enabled.
Information sources: Kernel.Docs.HAL.HAL_API, Kernel.hdr.OSEntries in CVS
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