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This section details the intricacies of the early hardware used by RISC OS. The first generation is commonly known as the Archimedes. The second generation is commonly known as the RiscPC range. The RiscPC range of computers were designed to take advantage of the more advanced features of the latest ARM processors, although many supporting chips were still proprietary chips designed by Acorn Computers Ltd.
RISC OS 3.5 up to RISC OS 4.x was used with this class of hardware. The information is specific to this type of hardware and version of RISC OS. The information is no longer valid or useful with RISC OS 5, but is available here for completeness.
The complete list of chips used with the more advanced RiscPC range of computers are as follows:
These chips are commonly known as the ARM chip set.
On some ranges of machines (such as the A7000), the functionality of these chips were included in the ARM processor itself (ARM7500 and ARM7500FE).
The ARM processor used with the RiscPC range of computers was one of the following:
Previous ARM processors were limited to accessing 64 MB of memory because of its 26-bit address bus. This limitation was removed on the newer ARM 600 processors, although it was possible to configure the processor to provide backwards compatibility. This change results in:
The ARM7500xx processor is a system-on-chip that integrates processor, video generator and most of the functions of the IOMD chip. The major differences are:
The ARM range of processors uses 32-bit words. Each instruction fits into a single word. It also has a 32-bit data bus so that complete instructions can be fetched in a single step.
As mentioned above, the newer ARM processors were updated to handle 32-bit address and data space. It was however possible to configure the processor to provide the original ARM address functionality. i.e. A 26-bit address bus.
The processor could be configured as any one of following:
RISC OS configures the control register of the ARM processor on start-up into 32-bit program and data space. This must not be changed.
Although 32-bit configuration is selected, much of RISC OS 3.xx still uses 26-bit modes for operation.
Because the processor is in 32-bit configuration, all exceptions (including Undefined Instructions and Software Interrupt) force the processor to a privileged 32-bit mode appropriate to the exception.
When configured for 32-bit program and data space the following processor modes are available:
Mode | Use for mode |
---|---|
User Mode | Mode normally used by applications |
User 26 Mode | 26-bit version of above |
Supervisor Mode (SVC) | A Protected mode for the OS |
Supervisor26 Mode (SVC26) | 26-bit version of the above |
Interrupt Mode (IRQ) | Used to handle peripherals when they issue interrupt requests |
Interrupt Mode (IRQ26) | 26-bit version of the above |
Fast Interrupt Mode (FIQ) | Used to handle peripherals that issue fast interrupt requests |
Fast Interrupt Mode (FIQ26) | 26-bit version of above |
Abort Mode (ABT) | Entered after data or instruction prefetch abort |
Undefined Mode (UND) | Entered when an undefined instruction is executed |
When configured for a 26-bit processor mode, the behaviour is the same as the ARM v2as architecture, with the following exceptions:
Twenty seven 32-bit registers are available on the ARM 2 and ARM 3 processor. Of those, only 16 are available within RISC OS. Some registers are shared across different modes, while others are not. The table below shows this:
User Mode1 | SVC Mode1 | IRQ Mode1 | ABT Mode | UND Mode | FIQ Mode1 |
---|---|---|---|---|---|
R0 | |||||
R1 | |||||
R2 | |||||
R3 | |||||
R4 | |||||
R5 | |||||
R6 | |||||
R7 | |||||
R8 | R8_fiq | ||||
R9 | R9_fiq | ||||
R10 | R10_fiq | ||||
R11 | R11_fiq | ||||
R12 | R12_fiq | ||||
R13 | R13_svc | R13_irq | R13_abt | R13_und | R13_fiq |
R14 | R14_svc | R14_irq | R14_abt | R14_und | R14_fiq |
R15 (PC) | |||||
CPSR | |||||
SPSR_svc | SPSR_irq | SPSR_abt | SPSR_und | SPSR_fiq |
1 Both 32-bit and 26-bit varieties
As mentioned earlier, the Program Counter and the Program Status Registers have both got their own registers. The Current Process Status Register (CPSR) is detailed below:
Bit | Contents |
---|---|
0 – 4 | Processor Mode Flag1 |
00000 = User26 Mode | |
00001 = FIQ26 Mode | |
00010 = IRQ26 Mode | |
00011 = SVC26 Mode | |
10000 = User Mode | |
10001 = FIQ Mode | |
10010 = IRQ Mode | |
10011 = SVC Mode | |
10111 = ABT Mode | |
11011 = UND Mode | |
6 | FIQ disable flag (set for disable) |
7 | IRQ disable flag (set for disable) |
28 | Conditional Flag – OverFlow (V) |
29 | Conditional Flag – Carry (C) |
30 | Conditional Flag – Zero (Z) |
31 | Conditional Flag – Negative (N) |
The VIDC20 chip controls the computer’s video and sound. The data is read from it’s 64-bit data bus using DMA control and then processed and converted into the necessary analogue signals to drive the video output displays and sound system. The VIDC20 can handle many more display and sound formats than the original VIDC chip found in the Archimedes Hardware. It can also read data from VRAM if installed in the machine, otherwise it reads from DRAM.
Data from the video buffer is converted and processed. They are as follows:
The VIDC20 chip can handle any pixel rate up to 110 MHz. The clock selected from one of three source, and can then be further divided by a factor between 1 and 8 (inclusive).
In addition it also contains a phase comparator which allows for a single clock to generate all the required frequencies for any display mode.
Up to eight separate channels of mono sounds is provided by the VIDC20 chip. The chip can work with 1, 2, 4 or 8 stereo channels using time division multiplexing to synthesize left and right outputs. Each channel can be assigned a stereo position (between left to right).
Data from the buffer is converted and processed. The following steps taken:
The cursor data controls a pointer than is 32 pixels wide, and an unlimited number of pixels high. The pixels can be transparent or can be any of three of the 28-bit wide palette. The cursor can be any shape within these limits.
The IOMD chip manages the memory, DMA and I/O within the hardware, and is a replacement to the original IOC and MEMC chips found in the Archimedes Hardware. The features of the IOMD are as follows: