Showing changes from revision #0 to #1:
Added | Removed | Changed
Entry | |
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R0 | 1 (Reason code) |
Exit | |
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R0 | Mask of valid exception enable bits |
All other registers preserved |
This call returns information about which trapped VFP exceptions are supported; i.e. which exceptions will generate an appropriate RISC OS error if the exception occurs while the exception enable bit is set.
The value returned in R0 corresponds to the exception enable bits in the FPSCR. For example, if bit 8 is set, it indicates that invalid operation exceptions can be generated by setting bit 8 of the FPSCR (the IOE bit). If the value returned in R0 is zero then it indicates that no exceptions can be generated (e.g. the VFP implementation in Cortex-A8 CPUs).
If this call returns an error due to being unimplemented then it indicates an old version of VFPSupport is in use which does not have the VFP support code implemented (VFPSupport versions prior to 0.06). In this case enabling exceptions may result in undefined instruction aborts occurring for any exception-generating instruction. In addition, undefined instruction aborts may also occur if the hardware is used outside of RunFast mode.