VIDC control list (changes)
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Programmer's Reference Manuals
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VIDC control list
Control lists are used with type 3 VIDC lists as a way of specifying extra settings. Each entry in the list is a pair of words, with the first word being the control index and the second word being the value. Under RISC OS 5, the defined values are:
| Control index | Description | Values |
|---|---|---|
| 1 | LCD mode | 0 => disable, 1 => enable |
| 2 | LCD dual panel mode | 0 => disable, 1 => enable |
| 3 | LCD offset register 0 | 0-255 |
| 4 | LCD offset register 1 | 0-255 |
| 5 | High res mode | 0 => disable, 1 => enable |
| 6 | DAC control setting | 0 => disable, 1 => enable (default) |
| 7 | RGB pedestals | bit 0 = R, bit 1 = G, bit 2 = B |
| 8 | External register value | 0-255 |
| 9 | H clock select | ? |
| 10 | R clock frequency | ? |
| 11 | DPMS State | 0-3 |
| 12 | ||
| 13 | Output format | 0 => analogue, 1 => digital |
| 14 | Extra bytes | 0+ |
| 15 | NColour value | see below |
| 16 | ModeFlags value | see below |
Notes
Control list items 3 and 4 are specified in a format suitable for writing to the VIDC20 LCD offset registers. Items 1, 5, 7 and 8 control various bits of the VIDC20 “external register” register. Similarly, items 2, 9 and 10 are only of interested to VIDC20 systems.
Control item 11 can be ignored by video drivers, as the appropriate DPMS state will be specified by the kernel on calls to GraphicsV 4.
Control item 12 controls whether a “full resolution” interlace signal is generated; i.e. an interlace sync signal is sent to the monitor, and the video DMA is adjusted so that the even field displays the even rows of the framebuffer, and the odd field displays the odd rows. But because the vertical timing parameters are in units of rasters, this means that the height of the framebuffer will be twice the vertical display size value given in the VIDC list. This is in contrast to the interlace sync/pol flag, which generates an interlace sync signal but does not alter the DMA. Because of the effect on the framebuffer size, control list item 12 must be handled correctly by drivers, even if it’s as simple as ensuring GraphicsV 7 rejects modes which are (or aren’t) interlaced.
Control item 13 is only relevant for Chrontel-based hardware.
Control item 14 specifies how many bytes there are between the end of one row and the start of the next. This value does not take into account the implicit skipping of every other row that must occur for interlaced displays; i.e. it’s specified as if a standard progressive framestore is used.
Control items 15 and 16 are used in combination with the Log2BPP value from the VIDC List Type 3 to indicate the pixel format. If left unspecified in the control list, the NColour and ModeFlags values will take the default values listed in the “Conversions to/from Log2BPP values” section of the Valid Mode Variable Combinations page.
Note that control items 12 and 13 have different meanings under RISC OS Select.
See Valid Mode Variable Combinations for a list of all valid NColour, ModeFlags and Log2BPP values currently understood by the OS.
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