Audio clock
===========
The SoC can either output the clock (master) or receive it (slave).

Master
------
CM_L4PER2_MCASP3_CLKCTRL selects the aux clock used for the master output, via the CLKSEL_AUX_CLK field.
0 = PER_ABE_X1_GFCLK
1 = VIDEO1_CLK
2 = VIDEO2_CLK
3 = HDMI_CLK

As the audio rate is unlikely to be a factor of the video pixel clock, VIDEO1_CLK and HDMI_CLK can't be used as they're driving the pixels. 

VIDEO2_CLK is free for use. Enabling M7_CLOCK_EN in PLL_CONFIGURATION2 of DPLL_VIDEO2 (and optionally setting M7_CLOCK_DIV) causes the MCASP block to run at that rate.

DPLL_ABE (the origin of PER_ABE_X1_GFCLK) is also unused, but the reference clock is the main system clock of 20MHz which can only satisfy the 24us period sampling rate using integer multipliers and dividers

     21.3333 = 64/3
     22.5792 = 14112/625
     24.5760 = 3072/125

Slave
-----
There's also a much more flexible PLL on the codec chip, which can take any reasonable 10's MHz input rate on MCLK and output (having set up the appropriate scalers) a 256xFs clock on its GPIO1, which in turn is input to the MCASP peripheral. This input pin is selected from the CM_L4PER2_MCASP3_CLKCTRL register's CLKSEL_AHCLKX field.